1. Field of the Invention
This invention relates to fabrication methods for integrated circuits and, more particularly, to a method, a system, and a memory storage medium containing instructions and/or data for implementing the method and the system for reducing variation in interconnect resistances of integrated circuits.
2. Description of the Relevant Art
Fabrication of integrated circuits upon semiconductor substrates ("wafers") involves numerous processing steps. For example, the fabrication of a metal-oxide-semiconductor (MOS) integrated circuit includes forming a gate dielectric, typically composed of silicon dioxide, on a semiconductor substrate doped with either n-type or p-type impurities. For each MOS field-effect transistor (MOSFET) being made, a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the semiconductor substrate. Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit. Modem high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections. Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels. Conductive plugs formed in the dielectric levels provide electrical connections between interconnects of differing levels.
A prevalent trend in integrated circuit fabrication is increasing the speed at which the circuit operates. The operating speed of a circuit refers to the time needed for a circuit output voltage to respond to a change in an input voltage. A major limiting factor of the operating speed or the circuit comes from an interconnect resistance R and a capacitance C between the interconnect and both ground and other interconnects. Such resistances and capacitances create RC time constants which characterize delays associated with the propagation of signals along the interconnect. Increases in operating speed of a circuit may be obtained, for instance, by reduction in resistance of its interconnects; however, there are other design constraints imposed upon the circuit that limit the amount the resistances may be reduced. For example, reducing the resistance of an interconnect increases the power dissipated as heat by the interconnect for a fixed voltage drop across the interconnect. If the amount of heat generated in the interconnect becomes too large, failure of the circuit may result.
A damascene process is a preferred method for forming interconnects in modern integrated circuits. A damascene process begins with forming trenches in an interlevel dielectric where the trenches correspond to the desired pattern of interconnects. The interlevel dielectric separates differing interconnect levels of the integrated circuit from one another and may have conductive plugs formed within to provide electrical connections between levels. Subsequently, an interconnect material typically a metal, is deposited within the trenches and upon the interlevel dielectric, and the interconnect material located outside of the trenches is then removed by chemical-mechanical polishing (CMP) to complete the formation of the interconnects. This is known as a single damascene process. Alternatively, a dual damascene process includes forming vias corresponding to the desired locations of conductive plugs in the interlevel dielectric in addition to forming trenches for interconnects in the interlevel dielectric. Interconnect material is then simultaneously deposited within the vias and trenches and upon the interlevel dielectric. Interconnect material located outside of the trenches is removed by CMP to finish forming the conductive plugs and interconnects. The damascene process is repeated for every interconnect level contained within the integrated circuit.
CMP is used to remove surface material from semiconductor wafers and to planarize Surfaces. A typical CMP tool is illustrated in FIG. 1. The tool shown in FIG. 1 is commonly referred to as a rotary CMP tool. Semiconductor wafer 10 is held in carrier 12 and is placed face down upon a polishing pad 14 that is attached to table 16. Both carrier 12 and table 16 may rotate and their rotational speeds are independently adjustable. A polishing fluid, typically a slurry, is deposited on the surface of polishing pad 14 through conduit 18. A polishing slurry consists of an abrasive-particle-containing fluid that may be chemically reactive with one or more of the materials on the surface of the wafer. The polishing slurry occupies the interface between wafer 10 and polishing pad 14. During the polishing process, carrier 12 and table 16 are rotated at angular frequencies .omega..sub.c and .omega..sub.t, respectively, while carrier 12 applies a force F downward on wafer 10, typically referred to as "down force". The polishing slurry may chemically react with the surface material of wafer 10 while the movement of wafer 10 relative to polishing pad 14 causes the abrasive particles contained in the polishing slurry to strip the reacted material from wafer 10. The amount of material removed by CMP is governed by several variables including down force, carrier rotational speed, table rotational speed, polishing time, polishing pad material, and polishing fluid composition, flow rate, and dispense location.
Another common type of CMP tool is the linear CMP tool. For this CMP tool, the rotating carrier pushes the wafer against a polishing pad that moves linearly underneath the wafer. For the linear CMP tool, the polishing pad is affixed to the surface of a belt whose motion is similar to that of a belt sander. The portion of the belt and pad directly underneath the wafer is supported by a fluid-bearing platen in which a flow of a fluid, such as air, is directed at the belt to counteract the down force exerted by the carrier. The polishing parameters for the linear CMP tool include down force, carrier rotational speed, belt speed, fluid-bearing platen pressure and flow rate, polishing time, polishing pad material, and polishing fluid composition, flow rate, and dispense location.
An interconnect resistance is determined by several factors including the dimensions of the interconnect and the conductive plug and the resistivity of the interconnect material. Each processing step used to fabricate interconnects will introduce variation in the interconnect resistance. For example, the trenches formed in the interlevel dielectrics of integrated circuits from different wafers or the trenches formed in different interconnect levels of the same integrated circuit will have small variations in their dimensions. The interconnect resistance R is given by R=.rho.l/A where .rho. is the resistivity of the interconnect material, l is the length of the interconnect, and A is the cross-sectional area of the interconnect. Variation in width or depth of the formed trenches will directly correspond to variation in the cross-sectional area of the interconnects which will give rise to variation in interconnect resistance. Interconnect resistance effects properties of the completed integrated circuit, such as operating speed. It is important, therefore, to control variation in interconnect resistance.
Variation in interconnect resistance can cause problems that may lead to failure of the integrated circuit. For instance, if the resistance is too small, excessive heat may be generated within the interconnect, as discussed above. Additionally, variation in resistance changes the time required for signals to propagate along the interconnect and may lead to timing problems both internal and external to the integrated circuit. Timing problems result when one or more signals arrive at a circuit element either earlier or later than expected.
The yield, which is the percentage of completed integrated circuits that are functional, tends to decrease with increasing operating speed. The operating speed targeted for the completed integrated circuit is determined by balancing the conflicting demands of increasing the yield and increasing the speed. Higher yield decreases costs associated with the fabrication process while integrated circuits of higher operating speed will generally be in greater demand by consumers. Variation in interconnect resistance might cause variation in operating speed; however, more applicable, variation in interconnect resistance may cause operating speed reliability issues. Completed integrated circuits may exhibit a distribution of operating speeds centered about an average operating speed. The average operating speed targeted is generally chosen such that the operating speed at the high end of the distribution will give a predetermined yield.
Modern fabrication methods minimize variation in interconnect resistance by minimizing the variation caused by each processing step. For example, trenches in the interlevel dielectric are typically formed by dry anisotropic etching of the interlevel dielectric. For different wafers and for different interconnect levels on the same wafer, the etched trenches will have some variation in their depth due to variation in a variety of etching parameters, including etching time. If variation in etching parameters, such as etching time, are minimized, variation in trench depth, which directly effects variation in interconnect resistance, will be minimized.
If the variation in interconnect resistance, for both interconnects of different wafers and of different interconnect levels on the same wafer, could be further reduced, the potential for excessive heating and timing problems would also be reduced. Additionally, a reduced variation in interconnect resistance will also narrow the distribution of operating speeds. The average operating speed targeted could then be increased since the narrower distribution of operating speeds would allow a higher average operating speed while still maintaining a given yield at the high end of the distribution. It is therefore desirable to develop an improved method for reducing the variation in interconnect resistance for interconnects of different wafers and for interconnects of different interconnect levels on the same wafer.